In a wireless communication system transmitting and receiving digital data, it is generally required to perform encoding/decoding processing of transmission/reception data signals. More specifically, on the transmission side, encoding processing such as adding CRC code to transmission data signals, scrambling processing, convolution encoding, and interleave (data rearrangement) processing is required. On the reception side, decoding processing such as de-interleave (inverse of interleave) processing on reception data signals, Viterbi decoding, de-scrambling processing, and CRC judgment processing is required.
In such encoding/decoding processing, calculations are performed with a bit unit or a byte unit. Thus, such processing may be referred to as bit/byte processing in some cases. Conventionally, such encoding/decoding processing has been achieved through mounting exclusive hardware circuits for each of the corresponding processing in order to deal with the encoding/decoding processing of a single wireless communication system at a high speed and with low power consumption.
Further, recently, there is an increasing expectation on a software wireless technique which makes it possible to deal with a plurality of wireless systems with a single device. Among the various kinds of normalized or standardized wireless systems, the contents of the encoding/decoding processing are similar to each other. However, the processing data unit, a part of processing parameters in calculations, the calculation order, and the like thereof are different.
However, to deal with the encoding/decoding processing of the plurality of wireless systems with the method of mounting the exclusive hardware circuit for each of the wireless communication systems, the corresponding numbers of exclusive hardware circuits are required for the number of the wireless systems to be dealt with. This causes an issue that the area of the circuits to be required and the cost thereof are increased. Further, it is also an issue that the flexibility for changes and expansions of the processing is low.
As a technique that can overcome such issue, depicted in Patent Document 10 to be described later is a technique which makes it possible to achieve both the high-speed characteristic and the power efficiency by dealing with a plurality of wireless systems through making the exclusive hardware circuit as the structure that can be set by various parameters. This is designed to deal with a plurality of wireless systems flexibly by constituting an exclusive processing engine to be resettable so as to be able to deal with a plurality of kinds of base band processing.
Further, as a technique similar to that, Patent Document 1 discloses a technique with which the exclusive hardware circuit is structured to be capable of setting operation modes and it is controlled from a central overall control processor to flexibly deal with system changes and the like.
Further, Patent Document 7 discloses a technique which performs processing on the encoding/decoding processing corresponding to a plurality of wireless systems with software by using a processor such as an exclusive signal processor (DSP) or the like. This is a technique which flexibly corresponds to various kinds of communication systems by achieving communication processing through using a typical signal processor and a DMA controller for increasing the speed of access to the memory in order to secure the flexibility.
Further, as a technique similar to that, Patent Document 2 discloses a technique which reduces memory access latency of a processor through providing an exclusive memory controller on the outside of a signal processing processor.
As other related techniques, Patent Document 3 discloses an image-processing signal processor capable of having a built-in magnification variable function while suppressing increase in the circuit scale by using a single memory port. Patent Document 4 discloses a logic integrated circuit capable of saving the space of the operation logic through structuring it to be capable of executing adding processing and multiplication processing in parallel.
Furthermore, Patent Document 5 discloses a communication system which sets a parameter regarding communications by a forward pilot tone and a reverse pilot tone. Patent Document 6 discloses a multiprocessor system which improves the efficiency of data transfer among a plurality of processors through compressing data locally before transferring it to a shared memory.
Patent Document 8 discloses a processor design tool and the like including an address generating unit which calculates an address every time according to a command. Patent Document 9 discloses a communication system that uses a processor that includes a register file used for calculation provided inside thereof.    Patent Document 1: Japanese Unexamined Patent Publication 2000-295309    Patent Document 2: Japanese Unexamined Patent Publication 2001-034573    Patent Document 3: Japanese Unexamined Patent Publication 2006-155637    Patent Document 4: Japanese Unexamined Patent Publication 2007-295128    Patent Document 5: Japanese Unexamined Patent Publication 2008-187722    Patent Document 6: Japanese Unexamined Patent Publication 2010-092499    Patent Document 7: Japanese Patent Application Publication 2002-541693    Patent Document 8: Japanese Patent Application Publication 2003-518280    Patent Document 9: Japanese Patent Application Publication 2005-516432    Patent Document 10: Japanese Patent Application Publication 2009-505608
The first issue is that it is not possible to flexibly deal with various kinds of encoding/decoding processing of a plurality of wireless communication systems in the encoding/decoding processing (bit/byte calculation processing) of a wireless communication apparatus.
The reason is as follows. Regarding the content of encoding/decoding processing in general, each processing among the plurality of wireless communication systems is similar in many cases. However, a part of processing parameters and calculation orders largely depend on the specifications of each of the wireless systems and the required calculation amount is relatively large. Therefore, conventionally, exclusive hardware circuits are mounted for each of the wireless systems.
However, in accordance with improvements in the processing capacity achieved due to the increases in the scale, the speed, and the like of recent system LSI, it is desired to achieve a wireless communication apparatus called a multimode wireless device or a software wireless device (SDR: Software Defined Ratio) capable of dealing with a plurality of wireless systems with a same encoding/decoding processing circuit. Further, it is also required to be the type capable of flexibly dealing with future specification changes and functional expansions.
The second issue is as follows. In a case where encoding/decoding processing (bit/byte calculation processing) is achieved by software processing by using a processor while placing a great importance on the flexibility in a wireless communication system, it is not possible to perform processing such as simultaneous calculations of a plurality of bits (bytes) at a high speed including memory access latency.
The reason is as follows. In order to process a single bit with the encoding/decoding processing in the wireless communication, information of a plurality of bits before and after that bit is required. Thus, it is not particularly an issue when executing the processing thereof in parallel with exclusive hardware circuits. However, in a case where it is to be achieved by software processing by using a processor while placing the importance on the flexibility and the expandability, it is difficult with a typical processor to simultaneously perform calculations of the encoding/decoding processing of a plurality of bits/bytes.
Further, in the case of the software processing by using the processor, the processor generally accesses to the memory, so that specific latency (the cycle number or delay time) is required. Therefore, the operability of the calculator is decreased for that and the processing time is increased, so that the processing cannot be performed at a high speed.
Note here that the processing amount of the encoding/decoding processing in the wireless communication generally depends on the required data transfer rate. The required data transfer rate is increased in the recent wireless systems, and the still lower power consumption is desired. Therefore, it is important to be able to perform high-speed communication with the still lower power consumption.
The technique capable of overcoming the issues described above is not depicted in each of the above-described Patent Documents. While it is possible with the technique depicted in Patent Document 10 to deal with changes in a part of the processing parameters of a calculation formula relatively easily by executing resetting, it is not possible to easily deal with changes in the processing data unit, the repeating number, the detailed calculation order, the processing order among each of the processing engines (exclusive hardware circuits), and the like.
In order to constitute it to be able to change the processing order and the like as well, the connection structure between each of the exclusive hardware circuits becomes extremely complicated so that the area of the device and the required cost are increased further. Also, it is still not possible to flexibly deal with future expected expansion of specifications such as changes in the calculation order and the like within processing engines.
Further, it is not possible with the technique depicted in Patent Document 1 to easily deal with changes in the detailed processing order, and the processing order and the like between each of the processing (exclusive hardware circuits) because of the same reasons.
In the meantime, with the technique depicted in Patent Document 7, the encoding/decoding processing of the wireless communication becomes special bit processing with the bit unit or the byte unit. Thus, the number of processing cycles is increased greatly with a typical signal processor compared to the case of the exclusive hardware structure that is capable of executing calculations of a plurality of bits in parallel. Further, while the flexibility for the changes in the processing is extremely high, the access latency from the processor to the memory, for example, comes to be in a state of performance overhead. Therefore, it is also difficult to increase the speed.
Even if a DMA controller is used for making an access to the memory, different cycles are required for a memory load/storing command and a calculation processing command in the case of the software processing executed by using the processor. Thus, the speed becomes slower compared to the case of the exclusive hardware processing, and the performance overhead of the bit shift processing and the like is required when the data unit to be processed by the processing and the data unit to be stored on the memory are different. For increasing the speed further in such case, it is necessary to increase the speed of the clock frequency. This results in increasing the power consumption and the heating value.
Further, with the technique depicted in Patent Document 2, the throughput at the time of data writing where the address and the data are transferred together while simply incrementing the address for an external memory is improved. However, the transfer cycles of the data corresponding to the addresses are different (2 cycles or more are required for reading out), so that the throughput at the time of reading out the data cannot be improved. Further, the addresses are for performing simple increment, so that it is not possible to deal with the special address order that is not the simple increment such as interleave/de-interleave processing in the coding/decoding processing of the wireless communication.
None of the other techniques depicted in Patent Documents 3 to 6 and Patent Documents 8 to 9 is designed to achieve encoding/decoding processing that can deal with a plurality of wireless communication systems at a high speed and with a simple circuit structure. Further, none of those is provided with the structure for that, so that such issues cannot be overcome naturally.
The object of the present invention is to provide the encoding/decoding processor and the wireless communication apparatus capable of achieving various kinds of encoding/decoding processing in a plurality of wireless communication systems at a high speed and with a simple circuit structure.